Multigigabit Serial Communication System Cable Design

There was an article in EDN magazine recently about designing equalization for cables in multi-gigabit serial digital communication systems [1].  The article was written by engineers from Redmere, a cable manufacturer that makes high speed actively equalized data cables.  The article really describes how high speed cables can be constructed for consumer application space where low cost is a primary constraint.  It describes some of the process variations that affect signal quality.  The article appears to be based on a white paper that is available from Redmere’s web site.  This information is very interesting and could be very useful for someone starting a multi-gigabit design.

Hearne, Kay and John Horan PhD. December 15, 2009. “Precision equalization and test bring high-performance, low-cost cabling.” EDN Magazine.

Via Tuning

Via tuning is the design process of optimizing the geometry of a printed circuit board via (plated hole that connects routing on one layer to another) to minimize the impedance discontinuity that the via presents in the transmission channel path.  A printed circuit board trace can be controlled in impedance by using microstrip or stripline routing structures, but the vias that connect between layers cause discontinuities, usually due to excess capacitance from the typical 50 Ohm trace structure.  The excess capacitance results in a drop in impedance and will cause some of the signal to reflect if the rise time of the signal is comparable to the delay of the via element.  I have done some work attempting to tune a via using the Ansoft HFSS 3D field solver with limited success.  These tools are complicated to use and very difficult to get absolute correlation with measurement.  It definitely takes some finely honed skills to get good results.  There was a series of posts on the SI Mailing list last year discussing some of the important aspects of via tuning in more detail (Re: Looking for good source of information regarding Via tuning).

Signal Integrity Reference Books – Multigigabit Channel Modeling and Power Integrity

There are plenty of well known signal integrity books that cover the basics.  Recently I have started to see some books become available on more advanced topics.  Here are some that I have discovered, although I don’t have any of these yet and can’t comment on how good they are.

  • Power Integrity Modeling and Design for Semiconductors and Systems, Authors: Madhavan Swaminathan and A. Ege Engin, Publisher: Prentice Hall PTR; 1 edition (November 28, 2007)]
    • book about power integrity – has been covered in a cursory way in many text books, but this book claims to be a more exhaustive coverage including how to do some of the detailed modeling
    • This book is available on Kindle!
  • Jitter, Noise, and Signal Integrity at High-Speed, Authors: Mike Peng Li, Publisher: Prentice Hall PTR; 1 edition (November 29, 2007)
    • This book is written by Mike Peng Li, formerly from Wavecrest where he pioneered the methods of measuring jitter and extracting RJ and DJ.  I’ve heard him speak at DesignCon and he is definitely an authority on the topic of jitter.
    • Also available on Kindle!
  • Fundamentals of Vector Network Analysis, Author: Michael Hiebel, Publisher: Rhode & Schwartz
    • The network analyzer is becoming an essential tool for the high speed digital designer.  It has traditionaly been the domain of the microwave engineer, and I have found that most knowledge about its use (like most test equipment for that matter) is not taught extensively in school or covered in books and is left to learn on the job from experienced engineers and making mistakes.  It’s nice to know that maybe a decent book exists to cover this complicated topic
    • Not available from Amazon.  It can be purchased directly from Rhode & Schwarz
  • Frequency-Domain Characterization of Power Distribution Networks, Authors: Istvan Novak and Jason Miller, Publisher:Artech House July 31, 2007
    • Istvan has been a frequent presenter/panelist at DesignCon and is well known in the industry for power delivery network design and characterization from his work at Sun Microsystems
    • Available on Kindle!

Another web site that contains a lot of very useful signal integrity and power integrity reference information is located at:

This is part of Istvan Novak’s web site, which according to the site is being moved to

High Speed Design Test Equipment Accessories

Accessories are an essential part of making good high speed digital design measurements.  A high end piece of test equipment is not useful if you cannot attach it to what you want to measure with a probe or fixture.  One company that I’ve discovered that has accessories in stock is Test Path.  They have active and passive scope probes out to high bandwidths, and TDR probes.  It appears that they mainly support Tektronix in the high end equipment area, but they also have many lower speed accessories for other manufacturers.

EEPROM Programming in Circuit and Signal Integrity

I recently had a situation where an EEPROM on a board had a custom program with the board’s serial number, board type, and unique checksums because of these.  The parts were already soldered on the boards, so I wanted a programming solution that would be fairly easy to change just a few bytes of a whole program and that would also be able to program the EEPROM on the board.  I did some internet searching and found several options, none of which seemed to be very reputable.  I decided to go with the TMS-120 from Triangle Micro Solutions.

One of the things about my application was that the EEPROM device in circuit was powered at 3.3V.  It could not tolerate 5V IOs.  Before connecting the TMS-120 to my circuit, I tested it first to see what IO voltage it was at.  I was expecting the outputs to be floating when high since they are supposed to be I2C and I thought the pull resistors would not be inside the TMS-120 but external.  Documentation was not clear on this.  It turns out the the TMS-120 has internal pull ups to 5V.  So I had to remove those pull ups before connecing to my circuit.  When I tried to connect the TMS-120 to my circuit with the long cable supplied by Triangle Micro Solutions, with pull ups to 3.3V it did not work.  I put a scope on the signals to see what was happening, and signal quality was very poor.  After many iterations of experimenting I discovered that it worked intermittently with external 5V pull ups and the long cable.  It works reliably with external 5V pull ups and a very short cable, but even with the short cable it still does not work at 3.3V.  This is a prime example of how signal integrity must be considered even for very slow interfaces like I2C.  I ended up having the desolder the EEPROM devices from my board, program them in a little SO-8 clamp fixture powered at 5V, and then solder them back on.  It works but definitely wasted a lot more of my time than I had planned.

Wavecrest now Gigamax Technology

Some how over the course of the past year Wavecrest went out of business without my even noticing it.  Wavecrest makes a type of signal integrity measurement device called a time interval analyzer.  This device measures the time between edges in a data or clock signal and uses that information to perform powerful jitter measurements.  Mike Li used to be part of Wavecrest and he was well known for presenting jitter theory papers at industry conferences such as DesignCon.  I seem to recall that he wasn’t with Wavecrest anymore the last time I saw a paper he presented.  I was always interested in their equipment, but have never been able to justify the expense for the level of usage that my company would have.  It appears that the assets of wavecrest were acquired by former employees who started a new company called Gigamax Technologies.  In checking their web page, I don’t think they have any really new products yet, but it is something that I will keep an eye on.  If anyone has had experience using the Wavecrest or Gigamax equipment, please post your experiences as a comment.

One other thought that I have is regarding the size of the signal integrity measurement equipment marketplace.  If signal integrity is truly a big design challenge, wouldn’t there be enough room in the marketplace for Wavecrest?  My impression was that their equipment was similar in cost to other types of equipment (maybe a bit more expensive), but very capable.  Are digital system designers bothering to make the engineering confidence measurements on their systems, or are they relying on the chip vendors to provide proven solutions that drop into standard applications with good high speed digital layout rules?  I would expect that the chip vendors would have to use this type of equipment to validate their chip designs, but perhaps system designers don’t bother.  May BER testing across temperature extremes and in environmental stress tests is sufficient to give confidence in a design without needing expensive SI test equipment.  Serial designs really do embed a lot of complexity into the communication link to become more tolerant of imperfections in the channel.  Is detailed signal integrity simulation, analysis, and verification becoming the realm of the chip vendors?  No one would argue that a bad system design could ruin a high speed serial communication link, but you don’t need detailed SI analysis to get a good enough design.

I don’t necessarily believe the above, but these are the questions swirling in my mind right now.  I’m interested to hear opinions from SI engineers but also from digital system designers.  How important is signal integrity simulation, analysis, and measurement to the system design process for multi-gigabit serial interfaces?

Agilent J-Bert Measurement Equipment

In the past I have written about a BERTScope from Synthesys Research .  This measurement equipment combines a bit-error-rate tester with precise voltage and timing sampling circuitry to allow the device to scan a received signal to measure the eye diagram.  Synthesys was the only such device for quite a long time, however I recently saw an announcement from Agilent of a new similar piece of equipment called the J-BERT.  Here are some basic specs for the new Agilent device:

  • N4903B J-BERT
  • Data rate options up to 7 Gbps or 12.5 Gbps
  • Built in clock recovery (BERTScope requires external CDR module)
  • BER testing
  • Eye diagram measurement
  • Jitter measurement with RJ/DJ separation

I haven’t had a chance to compare the performance, features, and price of this device with the BERTScope yet.  It definately seems like it could be a good alternative.

I did find one application note from Agilent that describes how this type of BERT scanning measurement equipment works titled “Eye Characterization on Idle and Framed Data Traffic: the Bit Recovery Mode“.  Perhaps more to come on this in a future article.