High Speed Design Test Equipment Accessories

Accessories are an essential part of making good high speed digital design measurements.  A high end piece of test equipment is not useful if you cannot attach it to what you want to measure with a probe or fixture.  One company that I’ve discovered that has accessories in stock is Test Path.  They have active and passive scope probes out to high bandwidths, and TDR probes.  It appears that they mainly support Tektronix in the high end equipment area, but they also have many lower speed accessories for other manufacturers.

EEPROM Programming in Circuit and Signal Integrity

I recently had a situation where an EEPROM on a board had a custom program with the board’s serial number, board type, and unique checksums because of these.  The parts were already soldered on the boards, so I wanted a programming solution that would be fairly easy to change just a few bytes of a whole program and that would also be able to program the EEPROM on the board.  I did some internet searching and found several options, none of which seemed to be very reputable.  I decided to go with the TMS-120 from Triangle Micro Solutions.

One of the things about my application was that the EEPROM device in circuit was powered at 3.3V.  It could not tolerate 5V IOs.  Before connecting the TMS-120 to my circuit, I tested it first to see what IO voltage it was at.  I was expecting the outputs to be floating when high since they are supposed to be I2C and I thought the pull resistors would not be inside the TMS-120 but external.  Documentation was not clear on this.  It turns out the the TMS-120 has internal pull ups to 5V.  So I had to remove those pull ups before connecing to my circuit.  When I tried to connect the TMS-120 to my circuit with the long cable supplied by Triangle Micro Solutions, with pull ups to 3.3V it did not work.  I put a scope on the signals to see what was happening, and signal quality was very poor.  After many iterations of experimenting I discovered that it worked intermittently with external 5V pull ups and the long cable.  It works reliably with external 5V pull ups and a very short cable, but even with the short cable it still does not work at 3.3V.  This is a prime example of how signal integrity must be considered even for very slow interfaces like I2C.  I ended up having the desolder the EEPROM devices from my board, program them in a little SO-8 clamp fixture powered at 5V, and then solder them back on.  It works but definitely wasted a lot more of my time than I had planned.

Wavecrest now Gigamax Technology

Some how over the course of the past year Wavecrest went out of business without my even noticing it.  Wavecrest makes a type of signal integrity measurement device called a time interval analyzer.  This device measures the time between edges in a data or clock signal and uses that information to perform powerful jitter measurements.  Mike Li used to be part of Wavecrest and he was well known for presenting jitter theory papers at industry conferences such as DesignCon.  I seem to recall that he wasn’t with Wavecrest anymore the last time I saw a paper he presented.  I was always interested in their equipment, but have never been able to justify the expense for the level of usage that my company would have.  It appears that the assets of wavecrest were acquired by former employees who started a new company called Gigamax Technologies.  In checking their web page, I don’t think they have any really new products yet, but it is something that I will keep an eye on.  If anyone has had experience using the Wavecrest or Gigamax equipment, please post your experiences as a comment.

One other thought that I have is regarding the size of the signal integrity measurement equipment marketplace.  If signal integrity is truly a big design challenge, wouldn’t there be enough room in the marketplace for Wavecrest?  My impression was that their equipment was similar in cost to other types of equipment (maybe a bit more expensive), but very capable.  Are digital system designers bothering to make the engineering confidence measurements on their systems, or are they relying on the chip vendors to provide proven solutions that drop into standard applications with good high speed digital layout rules?  I would expect that the chip vendors would have to use this type of equipment to validate their chip designs, but perhaps system designers don’t bother.  May BER testing across temperature extremes and in environmental stress tests is sufficient to give confidence in a design without needing expensive SI test equipment.  Serial designs really do embed a lot of complexity into the communication link to become more tolerant of imperfections in the channel.  Is detailed signal integrity simulation, analysis, and verification becoming the realm of the chip vendors?  No one would argue that a bad system design could ruin a high speed serial communication link, but you don’t need detailed SI analysis to get a good enough design.

I don’t necessarily believe the above, but these are the questions swirling in my mind right now.  I’m interested to hear opinions from SI engineers but also from digital system designers.  How important is signal integrity simulation, analysis, and measurement to the system design process for multi-gigabit serial interfaces?

Agilent J-Bert Measurement Equipment

In the past I have written about a BERTScope from Synthesys Research .  This measurement equipment combines a bit-error-rate tester with precise voltage and timing sampling circuitry to allow the device to scan a received signal to measure the eye diagram.  Synthesys was the only such device for quite a long time, however I recently saw an announcement from Agilent of a new similar piece of equipment called the J-BERT.  Here are some basic specs for the new Agilent device:

  • N4903B J-BERT
  • Data rate options up to 7 Gbps or 12.5 Gbps
  • Built in clock recovery (BERTScope requires external CDR module)
  • BER testing
  • Eye diagram measurement
  • Jitter measurement with RJ/DJ separation

I haven’t had a chance to compare the performance, features, and price of this device with the BERTScope yet.  It definately seems like it could be a good alternative.

I did find one application note from Agilent that describes how this type of BERT scanning measurement equipment works titled “Eye Characterization on Idle and Framed Data Traffic: the Bit Recovery Mode“.  Perhaps more to come on this in a future article.

High Speed Multimedia Interfaces and ESD

There was an article in the April 2009 issue of Conformity Magazine about input protection for high speed video type interfaces [1].  Video interface devices need to provide a lot of IO interfaces to external storage, networks, and video display devices.  Many of these interfaces are high speed and exposed to users in ESD unfriendly environments (ie carpetted living rooms).  Example interfaces are RCA I/O ports, VGA ports, IEEE 1394 Firewire ports, USB ports, eSATA ports, and HDMI ports.  The next generation of USB will be 5.0 Gbps and HDMI ports are already at 3.4 Gbps.  The article describes the characteristics of the ESD pulses that these devices must survive, but also points out another similar phenomenon of cable discharge that actually can be even more dangerous to the digital devices.  Cable discharge is refers to the discharging of any charge that is built up on a floating cable when it is plugged in to a device.  The total amount of charge is proportional to the length of the cable, and some of the interface cables can be quite long such as Ethernet that could be up to 100 m long.  The article goes on to describe the importance of considering the effect of the input protection devices on signal integrity.  It provides examples of some protection devices that are appropriate for use on high speed interfaces from Semtech.  Note that the article was written by Semtech employees so the focus was on Semtech parts only.

[1] Yang, Grace and Timothy Puls. April 2009. “Protecting Set Top Boxes from ESD and Cable Discharge Threats.” Conformity Magazine. Volume 14, Issue 4.

Wurth Electronics Common Mode Choke and Ferrite Bead Spice Models

I recently attended a lunch and learn presentation from Wurth electronics and learned a few interesting things.  First, there is a freely available RF simulator called RFSim 99 that can simulate with S parameters.  I found a copy of this at RF Globalnet (search for it under downloads on this site).  I played with it a little, and found it to be limited in value, but possibly useful for demonstrating and exploring S-parameters for a signal integrity engineer.  Another interesting thing that I learned was that Wurth has made a library of spice models of their common mode chokes and ferrite beads available in the LTSpice simulator from Linear Technology.  The models are available in an encrypted library that is included with this simulator.  At first I thought this might be useful for signal integrity simulation, especially for common mode chokes, however the models are encrypted and cannot be simulated in other SI spice tools.  It at least gives confidence that these models exist and possibly could be obtained by calling the Wurth Electronics sales rep.  Common mode chokes are used very often on differential signal lines such as LVDS in digital systems to limit EMI, but it is difficult to assess their affect on signal integrity without good simulation models.

Loose vs. Tight Coupling for Differential Pairs

Based on the influence of some signal integrity experts and my own intuition and simulation experience over the years in signal integrity, I am convinced that loosely coupled differential routing is usually the preferred method for routing differential pairs in a printed circuit board.  First a quick definition of loose vs. tight coupling:

Loose coupling – the ends of the differential pair are spaced far enough apart that the differential impedance is basically unaffected by the spacing between the pair and is basically equal to 2 times the single ended impedance of each line.  A reasonable rule of thumb for this is a spacing that is between 3x and 5x the distance to the nearest reference plane for striplines.

Tight coupling –  the ends of the differential pair are spaced close enough together that the differential impedance is affected by the spacing between the pair and the trace width must be narrrowed to maintain a differential impedance compared to the width of a singled ended line that is half the differential impedance.

The major benefits of loose coupling are:

  • maximum trace width for a given differential impedance in a given stackup (minimize skin effect loss)
  • further minimizes conductor loss due to current crowding on the side of the traces facing each other
  • ability to route around obstacles such as vias an break out of pin fields without worrying about maintaining constant spacing to prevent impedance changes (you don’t have to be as picky with the PCB designer’s routing, especially regarding length matching

The major benefit of tight coupling is:

  • routing density (you can pack more traces into a smaller area)

A second minor benefit of tight coupling is that it reduces the differential mode EMI from the trace, however for differential digital signaling, common mode EMI is a much more dominant factor and tight coupling does nothing to help this [3].  Note that lower noise immunity to crosstalk is not a major benefit of tight coupling.  In PCB structures, agressors rarely couple equally to both ends of a pair and thus crosstalk is nearly the same whether it is tightly or loosely coupled.

In general, the benefits of differential signalling that do not depend on loose or tight coupling are:

  • reduction in simultaneous switching noise (SSN) – equal and opposite currents into and out of a chip when the IO switches significantly reduce the power and ground bounce due to switching outputs
  • tighter noise margins and lower voltage swings
  • reduction of common mode EMI over single ended signaling

Some engineers are hard to convince (tight coupling for differential pairs is deeply ingrained in engineers minds, even though the context within which the ingraining occured is usually in twisted pair cables which have a completely different geometry and design constraints), so I have compiled some links to articles by Howard Johnson, a highly respected industry expert in signal integrity.

Here are links to each article along with descriptions (detailed citations are given at the end):

Article describing crosstalk effects in PCBs for diff pairs:
 
Article describing why loosely coupled diff pairs are okay:
 
Article describing how common mode radiation from diff pairs is the dominant effect so tight coupling beyond a 20 mil or so threshold does not provide much benefit:
 
Newsletter article describing all of the benefits of differential routing and why loose coupling is better than tight coupling.
 

[1] Johnson, Howard.  December 5, 2008. “Visualizing Differential Crosstalk.EDN Magazine

[2] Johnson, Howard. November 13, 2008. “Differential Coupling.EDN Magazine.

[3] Johnson, Howard.  December 12, 2002. “Reducing EMI with Differential Signaling.EDN Magazine.

[4] Johnson, Howard. November 11, 1998. “Differential Routing.” High-Speed Digital Design Online Newsletter. Vol. 2, Issue 30. [Internet, WWW, HTML]. Available: Available in .HTML format; Address: http://www.sigcon.com/Pubs/news/2_30.htm. [Accessed: 15 January 2009].

Low Cost 12 GHz Sampling Oscilloscope

Verification and testing of high speed digital designs requires a lot of expensive test equipment.  To design with 5.0 Gbps technologies such as PCI-E 2.0, a design team would need to have access to a 20 GHz TDR with advanced S-parameter software packages, and some type of oscilloscope for measuring the jitter and eye diagrams of the signals.  In addition, other equipment such as a Synthesys Research BERTScope could also be very useful in proving the robustness of the system and in tracking down root cause for certain signal quality issues and bugs.  Even renting all of this equipment is cost prohibitive for many design teams, and buying it is very hard to justify unless you have many projects to use the equipment each year.  I recently came across a low cost 12 GHz sampling oscilloscope from Pico Technology.  The PicoScope 9000 series has a couple of different models with different levels of functionality.  Neither of these models really has nearly all the features that you might want for signal integrity measurements yet, but the availability of these devices does provide hope that lower cost test equipment may be a possibility in the future for multi-gigabit serial interfaces.  The cost of the devices is approximately $10k to $12k.  One way these devices save cost is that they are meant to be used with an external PC that does all of the data processing and display.  The device consists of an analog front end to capture and store signals, and a digital interface to get the data into a PC.  Most high end oscilloscope equipment from the major manufacturers such as Tektronix, Agilent, and Lecroy basically contains a built in PC inside the oscilloscope box.  Everything is integrated into the box and the scopes even running PC operating systems such as Windows or Linux.  The major disadvantage of this system approach to oscilloscopes is that the PC hardware inside them becomes outdated very quickly, much more quickly than the analog oscilloscope hardware outlives its useful life.  It seems to make much more sense to partition the system at the oscilloscope to PC interface

Pico Technology also has a lot of other test such as other oscilloscopes that use external PCs (lower bandwidth real time scopes), and data loggers.  I have also seen similar type of equipment from other manufacturers for logic analyzers.

Package Design for Signal Integrity

I have been doing some research into signal integrity design for electronic packages.  Basically electronic package design involves creating a container to enclose an integrated circuit (IC) or ICs to make it robust enough for attachment to a printed circuit board through a soldering process.  I view this field as important to high speed digital design because system in a package seems to have a lot of promise for increasing system performance.  In the future, digital engineers may design custom systems in package similar to the current system on a board process where multiple components are integrated together on printed circuit boards.  There are many different types of packages, but the design is cross discipline involving the following aspects:

  • electrical schematic level design to create a netlist for routing (especially for system in a package designs with multiple dies in a single package)
  • electrical design or power distribution and interconnections (signal integrity concerns)
  • thermal design (making sure the heat generated by the IC(s) can be dissipated and temperatures kept below critical maximum die temperatures
  • mechanical design of package structures to ensure stresses and strains in the assembly process and during normal operation do not cause device failure
  • materials design (choosing materials that meet the requirements of performance, reliability, and regulations)
  • PCB cad design (layout and routing of the ICs inside the package to create engineering drawings to be used in the fabrication of the package)

A package design group would require all of these skills, as well as tight integration with the package assembly process.

Tool Vendors

These are some tools that I came across in my research that seem appropriate for the electrical design aspects of package design.  Some of these vendors may also provide thermal and mechanical tools for use in package design as well.  Please respond to this post with any other tools that I missed, as I’m sure the list is not exhaustive.

Apache Design Solutions – PakSi-E – This tool does 3D field solution for package designs.
Supports extraction from Cadence Allegro, Encore BGA, Mentor Graphics MCM Station, and Zuken CR-5000.
Output results are RLGC matrices,  spice subcircuits, whole package IBIS models, w-element models, SDF delay models, SI parameters (S, Y, Z, crosstalk ratio, etc.), as well as current density and voltage drop for power and ground pins.

Sigrity – CoDesign Studio – Tools including Speed 2000, XcitePI, and PowerSI for doing package and IC codesign.

Cadence Allegro Package SI – Tool that provides some SI interface analysis capabilities to the Cadence Allegro package design tools.  It requires an external 3D field solver engine though from a third party such as Apache.

Ansoft SI Wave – Package design tool, can be used stand alone or also with full 3D field solver HFSS from Ansoft.  Interfaces with package layout tools.

Ansys IceMax – 3D field solver for package design.  Now that Ansys owns Ansoft, I wonder what strategy they will follow with this and overlapping HFSS and SI Wave tools.

Online Webinars

Here are some online resources that I came across in my research.  Again this list is not very complete and I welcome additional suggestions.

References

[1] Cole, Brad. September 23, 2008. “Signal integrity modeling tools critical to high speed IC package design.”  Planet Analog.

[2] Lau, John, C.P. Wong, John L. Prince, Wataru, Nakayama. 1998. Electronic Packaging Design Materials, Process, and Reliability. McGraw-Hill: New York, NY.

Ansoft HFSS Forum

Ansoft HFSS is a very powerful 3D field solver tool.  It is a general purpose field solver tool that can be used for any electromagnetic field application.  It is used in signal integrity design for simulating and optimizing transmission channel structures for digital signals in printed circuit boards.   Even though the tool is extremely powerful, it is also very hard to learn how to use, and even harder to use effectively with good correlation between simulation and reality.  At industry conferences there are often papers presented where good corellation is obtained between simulation and measurement.  Jason Miller, an HFSS expert user from Sun Microsystems has created an online forum for Ansoft HFSS users to share knowledge and techniques.  The forum is described in a post in the Signal Integrity Mailing List.  So far there hasn’t been much posted in this forum, but it has great potential to help users become more proficient in using this powerful, yet complicated tool.

One other thing that I wanted to mention about Ansoft HFSS related to signal integrity simulation is that Ansoft has created a via modeling wizard for use with the tool that simplifies the process of creating a model of a via.  Optimizing via transitions in a PCB to minimize the impedance discontinuity is one thing that 3D field solvers can be very good at since it is clearly a 3D problem.  The wizard provides a GUI to quickly create a via and analyze effects from parameters such as anti-pad size, diameter, and backdrilling.  It can also create differential via models.  This tool is available to all Ansoft HFSS users. and is easy to use.  I hope Ansoft comes out with many more signal integrity related wizards for use with HFSS, as it would make the tool more usable by digital hardware engineers instead of dedicated experts.

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